The embodiment of the invention relates generally to reducing power grid noise in a processor and particularly to reducing power grid noise in a processor while minimizing performance loss.
In high performance processors or other integrated circuits (ICs), to increase the processing performance of the processor, the processor chip design typically includes one or more of one or more processor cores and one or more pipelines connecting the processor cores. In addition, in a high performance system, processor system designs often include multiple chips sharing a common supply rail of a power distribution network providing a supply voltage. As the number of processor cores on a same chip or across multiple chips, all sharing a common supply rail, increases, the number of circuits that switch per clock cycle also increases.
In a processor there is noise generated by circuit switching activity at each clock cycle by nodes, busses, and other circuit components sharing a common supply rail. One result of noise generated by circuit switching activity, also referred to as power grid noise or di/dt noise, is that a sudden increase in noise will induce a droop in the supply voltage to the common supply rail of the power distribution network. A sudden, large droop in the supply voltage slows down the circuit response and therefore could cause timing errors on the logical circuit.
To reduce the noise generated by circuit switching activity, a processor may include decoupling capacitors positioned near the switching circuits of the processor cores, where the decoupling capacitors act as a charge reservoir and help reduce noise on the power distribution network as circuit switching activity increases. The supply voltage droop ΔV induced by an increase in circuit switching activity at the chip level is proportional to ΔI sqrt(L/C), where ΔI is the increase in current required by chip level switching circuits on the common supply rail, L is the inductance from the chip level circuits to printed-circuit-board or package level, and C is the summed chip level capacitance of the circuits on the common supply rail. Since many cores can be activated simultaneously, one limitation of implementing decoupling capacitors to reduce noise is in the case where there is a sudden burst of activity on one or more processor cores, increasing the current, and because ΔI is directly proportional to the number of cores on the common supply rail, the sudden increase in ΔI outweighs the noise reduction by the charge reservoirs of the decoupling capacitors, triggering a voltage droop. The risk for such a voltage droop is particularly high if several processor cores are leaving an idle state at the same time.
To address this problem US 2014/0181554 A1 proposes a multi-core data processor including multiple data processor cores each having a power state controller and a circuit connected to the data processor cores. An operating system causes processor cores to enter an idle state if a barrier for a thread run by the respective processor core encounters a barrier and keeps track of the idle states of the processor cores. The circuit of the known multi-core data processor provides a control signal in response to power states of multiple data processor cores. Only in response to a release signal each power state controller changes the power state from an idle state to an active state in dependence on the control signal.